a. Field of the invention
The present invention pertains to an amplifier, and more particularly it relates to an amplifier designed so that no excessively large rush current flows to the FET of its power amplifying circuit at the time of starting this amplifier, i.e. when this amplifier is connected to a power source.
B. Description of the prior art
Recently, there has been the tendency that field effect transistors (hereinafter to be referred to as FET's) are preferably employed as the power amplifying element in the power amplifying circuit of an amplifier instead of bipolar transistors. In its zero bias state, the bipolar transistor is kept nonconductive even when a voltage is applied between its collector and emitter circuits. An FET, on the other hand, has the nature that, whenever a voltage is applied between its drain and source electrodes, there flows a drain current in the zero bias state of the FET.
As a result, in an amplifier in which is employed FET's as its power amplifying elements, it should be noted that there flows an excessively large current through the FET's at the time the amplifier is put to work, i.e. when the amplifier is connected to a power source, and that, accordingly, there could often arise problems such that the FET's are broken or the characteristics of the FET's become deteriorated. Such problems would most frequently arise where an amplifier is of the type that the power amplifying circuit and the drive circuit of the amplifier are operated by separate power sources, respectively.
These inconveniences of the prior art will hereunder be described in further detail by referring to FIG. 1 which depicts a conventional type amplifier.
In FIG. 1, the FET's Q12 and Q13 of a power amplifying circuit are of the so-called single-ended push-pull configuration. The drain electrodes of these FET's Q12 and Q13 are connected to a first positive power source +EC1 and to a first negative power source -EC1, respectively. Also, the commonly connected sources of the FET's Q12 and Q13 are connected to a load RL. A bipolar transistor Tr11 constitutes the drive circuit for driving the FET's Q12 and Q13 of the amplifying circuit. The emitter circuit of this bipolar transistor Tr11 is connected to a second negative power source -EC2. The collector circuit of the bipolar transistor Tr11 is connected to a second positive power source +EC2 via resistors R11 and R12. This drive circuit includes a bias circuit for generating the gate-bias voltages of the FET's Q12 and Q13 of the power amplifying circuit. The voltages produced at the opposite terminals of the resistor R11 are supplied to the gates of the FET's Q12 and Q13 as the bias voltages.
The output voltages of the second positive power source +EC2 and the second negative power source -EC2 normally are stabilized so that these stabilized output voltages serve to eliminate the bias fluctuations of the FET's Q12 and Q13 and the ripple effect of the power sources. Accordingly, the second positive power source +EC2 and the second negative power source -EC2 are such that, when these two power sources are put to operation, their output voltages do not quickly rise to a predetermined value. A relatively lengthy period of time is consumed before these output voltages gain the predetermined value. On the other hand, it is usual that the output voltages of the first positive power source +EC1 and the first negative power source -EC1 reach a predetermined value in a relatively short period of time after they are put to operation. For this reason, in the stage of the amplifier immediately after the amplifier is started, there is immediately applied a predetermined voltage between the drain and source electrodes of the FET's Q12 and Q13 of the power amplifying circuit. However, the build-up of the output voltages of the second positive power source +EC2 and the second negative power source -EC2 are delayed so that the drive circuit is not applied with a predetermined voltage. Accordingly, the FET's Q12 and Q13 are given substantially a zero gate bias state. As a result, there will flow an excessively large or rush current to the FET's Q12 and Q13 which are usually of a depletion mode. When this excessively large or rush current flows to these FET's they are heated up and may be destroyed or the heating of these FET's may cause deterioration of the FET's Q12 and Q13.